Integrated circuits are made up of millions of active devices formed in or on a substrate such as silicon or gallium arsenide. The active devices are typically isolated from each other using silicon-containing dielectric materials such as polysilicon, single-crystalline silicon, silicon dioxide, silicon-containing low-k inorganic and organic materials, phosphosilicate glass, borophosphosilicate glass, and the like. The active devices are usually formed in multiple layers that are interconnected to form functional circuits and components. Interconnection of active devices is typically accomplished through the use of well-known multilevel interconnection processes such as the process disclosed in Chow et al., U.S. Pat. No. 4,789,648.
Copper, aluminum and tungsten are preferred metals used to fabricate integrated circuits. These metals, however, have a tendency to diffuse into conventional silicon-containing dielectric materials. Once silicon-containing dielectric materials have been contaminated with metal atoms, the dielectric constant is adversely affected and the integrated circuit may cease to function properly. Therefore, a barrier layer or liner film must be applied to the silicon-containing dielectric layer in order to prevent metal diffusion.
One of the presently preferred methods of fabricating integrated circuits having metal wiring and interconnects, which are also known as damascene structures, generally comprises providing interconnected metal wiring or metallization patterns in a discrete layer of silicon-containing dielectric film. The silicon-containing dielectric layer is etched or otherwise processed to pattern a series of trenches and holes therein. A thin barrier layer, generally not more than approximately 300 □ (30 nm) thick, is then deposited over the silicon-containing dielectric layer. When the metal used to form the wiring pattern is copper, the preferred barrier layer comprises a thin film of tantalum and/or tantalum nitride. When the metal used to form the wiring pattern is aluminum or tungsten, the preferred barrier layer comprises a thin film of titanium and/or titanium nitride. Such barrier layers are commonly deposited by physical vapor deposition, which is also known as sputter deposition, or they may be deposited by chemical vapor deposition. The barrier layer coats the surfaces of the trenches and holes as well as the upper surface of the silicon-containing dielectric layer to prevent metal diffusion and also to provide good adhesion between the metallization layer and the silicon-containing dielectric layer. A layer of metal approximately 3,000–15,000 Å (300–1,500 nm) thick is then deposited over the barrier layer so as to completely fill the trenches and holes. The filled trenches thus form a network of metal lines whereas the filled holes form vias or interconnects. The final step in the process of fabricating an integrated circuit, which is also known as a damascene process, is removing the metal layer and barrier layer down to the upper surface of the silicon-containing dielectric layer leaving only the metal filled trenches and holes. This is typically accomplished by chemical-mechanical polishing.
In a typical chemical-mechanical polishing process, the surface of the damascene structure is placed in direct contact with a rotating polishing pad at a controlled downward pressure. An abrasive and chemically reactive solution commonly referred to as a “slurry” is present between the pad and the surface of the damascene structure during polishing. The slurry initiates the polishing process by chemically reacting with the surface of the metal and/or barrier layer being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate and the presence of the slurry at the film/pad interface. Polishing is continued in this manner until the desired metal and barrier layer are removed.
The composition of the slurry is an important factor in the chemical-mechanical polishing. If the chemical agents and abrasives in the slurry are selected properly, the slurry can be tailored to provide effective polishing of metals and barrier layers at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion. Furthermore, the polishing slurry can preferably provide controlled polishing selectivities to other materials used to construct the damascene structure.
One of the problems with known chemical-mechanical polishing slurries used to remove barrier layers in damascene structures is that they tend to remove the underlying silicon-containing dielectric layers at a relatively high rate. This makes it very difficult to remove all of the barrier layer without eroding or otherwise damaging the underlying silicon-containing dielectric layer. Because of this problem, in many instances the polishing of the barrier layer is stopped too soon, which results in a portion of the barrier layer remaining on the damascene structure. Conversely, if polishing of the barrier layer is stopped too late, the result is that significant portions of the underlying silicon-containing dielectric layer are removed. In either circumstance, the integrity and functionality of the integrated circuit can be adversely affected.
A need exists for a chemical-mechanical polishing slurry for use in removing barrier layers from damascene structures that reduces and/or eliminates this problem. Such a chemical-mechanical polishing slurry would preferably remove barrier layers at a high enough rate to insure acceptable throughput while at the same time avoid removing or damaging the underlying silicon-containing dielectric layers.